Issues in logic synthesis for delay and bridging faults

The synthesis and testing issues for certain nonclassical faults (delay and bridging faults) are considered. Cost versus performance tradeoffs in synthesizing circuits which are robust delay fault testable are first examined. A new type of scan latch design is presented for robust delay fault testability of sequential circuits. The testability of bridging faults in combinational logic is also addressed. Tests are generated using implicit don't cares obtained for the circuit during the synthesis process. A PODEM-based algorithm has been developed for fast detection of a class of bridging faults.<>