A 100 MHz 40-tap programmable FIR filter chip

The design and implementation of a single-chip programmable 40-tap finite impulse response (FIR) filter in 0.9 mu CMOS technology is described. The chip is fabricated and tested at sample rates up to 100 MHz. It performs over four billion multiply-add operations (12*10 bit multiplications and 26-bit additions) per second in less than 22 mm/sup 2/ of silicon area while dissipating about 3.1 W of power.<>