IC spot-defect and fault semantics-a unified framework

A theoretical framework to model spot defects with their related faults in any IC technology is presented. The defect models are unintended geometrical variations introduced in the shape of the patterns of the IC. The transcendence of a defect is determined by the impact that it has at several levels of abstractions. This impact is called a fault. The framework is a mathematical construction which encompasses a hierarchical fault modeling that avoids irrelevant information at every level of abstraction. The framework includes consistency requirements on fault modeling which can be used to analyze the origins and reasons of malfunctions in production chips.<>