DSMLock: Low Overhead Logic Locking for System Security with Design Space Modeling

Integrated circuits (ICs) are increasingly manufactured in untrusted facilities, raising concerns regarding intellectual property (IP) protection. Logic locking has emerged as a solution to address these concerns by corrupting a circuit’s functionality unless a correct secret key is applied. However, prior work has shown that system-level phenomena can undermine module-level locking strategies, motivating the need for system-aware logic locking configuration. In this paper, we propose DSMLock, a design space modeling algorithm that identifies favorable logic locking configurations for arbitrary ICs by simulating a small, carefully selected subset of the design space to generate system-level predictive models. DSMLock efficiently identifies promising solutions that meet arbitrary, designer-specified security goals with minimal power/area overhead. To evaluate the proposed algorithm, we perform two experiments. First, an exhaustive simulation of the considered logic locking design space for a RISC-V ALU demonstrated that our models achieved an average R² > 0.99 across all design objectives and identified a locking configuration within 96% of the global optimum after simulating less than 3.6% of the design space. Second, when comparing DSMLock against three module-level locking approaches for a RISC-V processor and an APRSC communication interface, we evaluated two cost functions: power-focused and area-focused. Under the power-focused cost function, DSMLock achieved average power reductions of 42.4% and 6.0% for the locked modules in the RISC-V and APRSC designs, respectively. Under the area-focused cost function, DSMLock achieved average area reductions of 6.1% for the RISC-V locked modules and 3.3% for the APRSC locked modules. Moreover, of the 3 evaluated locking approaches, DSMLock was the only approach to meet all specified design objectives across both design objectives for all test cases.