A 12-Bit 600-MS/s Pipelined ADC With Two-Stage High-Gain Dynamic Amplifier in 28-nm CMOS

This paper presents a 12-bit pipelined analog-to-digital converter (ADC) featuring a two-stage high-gain dynamic amplifier (DA) architecture. The first stage employs a gain-boosting floating inverter amplifier (GB-FIA) to achieve high DC gain and power efficiency. By using a current-controlled delay cell, the partial FIA (P-FIA) based second stage with input dynamic bias could ensure stability, faster slewing behavior and power efficiency for the residue amplifier (RA). Additionally, a modified bootstrapped switch (BTS) with improved start-up speed reduces sample-dependent nonlinearity in the multiplying digital-to-analog converter (MDAC) during the non-overlapping phase. Fabricated in a 28-nm CMOS process, the prototype ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 58.9 dB at a Nyquist-rate input with a 600 MS/s sampling rate. Operating at a 0.9-V supply, it consumes 15.6 mW, achieving a Schreier figure-of-merit (FoM) of 161.8 dB. Notably, without gain calibration, the ADC maintains a spurious-free dynamic range (SFDR) exceeding 77 dB across the Nyquist bandwidth, attributed to its sufficient loop gain, wide output swing, and dedicated reset phase.