A Fault-Aware Architecture for Reliable Sparse Matrix Multiplication

With the advancement of Artificial Intelligence (AI), the reliability of AI accelerators has become increasingly critical. Moreover, sparse matrix multiplication has become a fundamental primitive of deep learning, which can enhance the efficiency of model training and inference. However, reduced redundancy in sparse pruning models increases their vulnerability to permanent faults. Thus, ensuring both efficiency and reliability in sparse matrix multiplication is critical. Most existing reliable AI accelerators are tailored for general matrix multiplication, leading to suboptimal efficiency when handling sparse matrix multiplication and incurring substantial hardware overhead to support fault tolerance. To address this, we propose a hardware-software co-design fault-aware architecture for reliable sparse matrix multiplication, with negligible additional area overhead. Specifically, based on the unstructured-pruned matrix, we propose fault-aware reordering for sparse matrix at the algorithmic level, which mitigates faults through fine-grained data scheduling, and further enables parallel computation by employing a sparsity-aware merging strategy. At the hardware level, we design a fault-tolerant sparse matrix accelerator based on an optimized systolic array for sparse matrix, incorporating bypass paths for faulty PEs. Experimental results demonstrate that our architecture can tolerate a fault rate of up to 10%, achieving a recovery efficiency improvement of 1.89× ∼ 7.11× compared to existing methods, with minimal area overhead.