A high speed pipelined CMOS accumulator for implementing numerically controlled oscillators

A high-speed pipelined CMOS accumulator which is designed for implementing a rate-multiplier-type oscillator is introduced. In such an oscillator the carry overflow of an accumulator is simply utilized as the output. The approximation to the rate frequencies, the circuit realization, and the ways to update frequencies are discussed. SPICE simulations show that the utilizable clock rates are over 400 MHz for a 2- mu m p-well chip and over 650 MHz for a 1.6- mu m n-well chip.<>