A simple short-channel MOSFET model and its application to delay analysis of inverters and series-connected MOSFETs

A simple short-channel MOSFET model is proposed and applied to the delay analysis of CMOS inverters and series-connected MOSFET structures (SCMSs). The model is implemented in SPICE3 and shown to enhance the simulation speed. The model parameters for this model can be easily obtained. A delay analysis of the SCMS is carried out in the submicron region, and it is shown that the delay ratio ((delay of NAND/NOR)/(delay of inverter)) becomes smaller as channel length gets shorter. For example, if the maximum number of series-connected MOSFETS is considered to be five in 2- mu m designs, then the number can be increased to 6 approximately 7 in the submicron circuit design. In the typical cases in VLSI designs, the delay ratio for N-SCMSs is much less than N/sup 2/.<>