A Gain-Boosting Reference-Double-Sampling PLL Using Tail-Feedback VCO with Implicit Common-mode Resonance

A type-II phase-locked loop (PLL) is presented by using a reference-double-sampling phase detector (RDSPD) and the proposed active gain-boosting cell (GBC). By using the RDSPD and the GBC, the equivalent gain of the phase detector is enhanced to suppress the in-band phase noise. In addition, a tail-feedback voltage-controlled oscillator with implicit common-mode resonance is presented to achieve low output phase noise. This PLL is fabricated in a 28 nm CMOS technology, which occupies an active area of 0.181 mm². Operating at 6.4 GHz from a 1 V supply, its power consumption is 14.83 mW. Experimental results demonstrate that this PLL achieves a root-mean-square jitter of 77.3 fs, which integrates the phase noise from 10 kHz to 100 MHz. The calculated figure of merit (FOM) is -250.5 dB.