Verilog Code Generation of Hierarchical Design Using LLMs

Creating RTL hierarchy and generating module-by-module Verilog code, both through a large language model (LLM), are presented. (1) For RTL hierarchy, LLM is prompted to identify a list of sub-modules, given the header and function description of a top-module. The sub-hierarchy is then iteratively constructed in a top-down fashion, while the sub-modules’ headers and function descriptions are created and refined. (2) Verilog code is generated in bottom-up fashion. Test scenarios are compiled and used to generate Verilog testbenches, identify reference module output signals, and generate Verilog code. The Verilog simulator receives all three and performs compilation and functional simulation. Any compilation- or functional-errors trigger the LLM to refine the Verilog code, with error messages provided.Experimental results show that our approach can create accurate RTL hierarchies more often than a single LLM prompting does (6 vs 0 out of 10 trials), while more sub-modules are identified (12.6 vs 6.4 on average). The correct Verilog code is generated even for a complex example such as AES with the proposed code generation procedure.