A 500 MSps 9-12b Programmable Cryo-CMOS SAR ADC for Quantum Computing

This paper presents a cryogenic-compatible, dual-channel time-interleaved successive approximation register (SAR) ADC designed for qubit state readout circuits. Operating at 4K, the ADC achieves a sampling rate of 500 MSps. To address the unique challenges posed by cryogenic temperatures, the design includes calibration mechanisms for comparator mismatch and clock skew between channels, as well as redundant bits to correct errors. Fabricated in a 28nm CMOS process, the ADC features an adjustable resolution from 9 to 12 bits, providing greater application flexibility. At 4K and 500 MSps, the ADC achieves 46.45 dB spurious-free dynamic range (SFDR), 41.63 dB signal-to-noise and distortion ratio (SNDR) and 64.27 dB 3rd-order intermodulation suppression (IMD3) near the Nyquist band with 9-bit resolution. This design ensures stable and reliable performance in cryogenic environments, thereby enabling large-scale qubit readout with high fidelity and efficiency in cryogenic environments.