Design and Analysis of Low Power and High Speed 8-Bit ALU Using Hybrid Full Adder

This work uses an optimized Modified Gate Diffusion Input (MGDI) technique to design a low-power, high-speed, 8-bit Arithmetic Logic Unit (ALU) that is implemented in 90 nm CMOS technology. The suggested ALU uses a hybrid full adder based on XOR and MUX logic to combine arithmetic and logic functions in a small package. Important parts like logic gates and MGDI-based multiplexers drastically cut down on the number of transistors and power usage while preserving full logic swing and steady operation. Simulation results show significant improvements over standard GDI-based and conventional CMOS ALUs, such as a 26.9% reduction in delay, a 36.8% and 58.6% reduction in power consumption for 1-bit and 8-bit ALUs, respectively, and a reduction of up to 50% in transistor count. The suggested MGDI-based ALU is a promising option for next-generation low-power applications in energy-efficient VLSI design, portable electronics, and embedded systems because of these improvements.