Performance Metrics Comparison of 8-Bit Adder Architectures in 45nm CMOS

This paper presents a comparative study of delay, power consumption, area efficiency, and a review of six different architectures of adders, namely Brent-Kung, Ladner-Fischer, Han-Carlson, Kogge-Stone, Sklansky, and Sparse Kogge Stone Adder. An adder is one of the basic building blocks of a digital circuit, which is used in a wide range of arithmetic calculations in microprocessors, ALUs, and signal controllers. Adders play a critical role in the digital computing environment where addition, subtraction, and multiplication must be performed as efficiently as possible. Parallel prefix adders are an example of how modern adders like Brent-Kung and Ladner-Fischer work. The study derives thorough simulations and analyses through Cadence Virtuoso, which analyzes the delay, power consumption, and transistor population of each adder to showcase their merits and demerits. The study is confined within the scope of design simulation and measurement of performance on the different architectures of the adders based on 45 nm technology, which aims to provide a complete analysis for choosing the most appropriate designs for effective high-speed digital systems.