High-Resolution Time Amplifier-Based Time-to-Digital Converter

High-resolution Time-to-Digital Converters (TDCs) are crucial in telecommunications, instrumentation, and navigation, particularly in time-of-flight systems such as LiDAR and 3D imaging. This work presents a high-resolution Time Amplifier-based TDC using a multistage approach. The study involves evaluating existing TDCs, designing an optimized architecture, and comparing it based on resolution, power consumption, and area efficiency. The design, implemented in CMOS GPDK 90nm using Cadence Virtuoso and simulated in Cadence Spectre, includes Coarse, Middle, and Fine Stages with a Selection Block. The architecture achieves stage-wise resolutions of 190 ps (Coarse), 9 ps (Middle), and 2.55 ps (Fine). With the integration of a divide-by-2 frequency divider, the final resolution is further improved to 0.7 ps, representing a 72.6 % enhancement over existing conventional fine-stage TDC architectures. This refined resolution minimizes quantization errors, making the design well-suited for ultra-precise timing applications such as time-of-flight measurements and highspeed data converters.