Efficient multiplier design based on multi-radix booth encoding

This paper presents optimized 16-bit signed multipliers implementing radix-4, radix-8, and radix-16 Booth algorithms in both serial and parallel configurations. The design features an improved sign extension method and truncated Ladner-Fischer adders for efficient partial product generation and compression. Enhanced Booth encoding and partial product preprocessing contribute to improved overall performance. Experimental results show significant improvements in area utilization, power consumption, and power-delay product, particularly in radix-4 and radix-16 implementations. The design proves suitable for applications demanding efficient multiplication operations.