Novel FPGA Technology Mapping for Dual-Output LUTs: Methodology and Application

Dual-output look-up tables (LUTs) are supported by modern commercial Field-Programmable Gate Array (FPGA) architectures. Existing technology mapping usually generates multi-output LUTs by merging single-output LUTs. However, these mapping solutions often fail to fully leverage the multi-output capability. This paper proposes a novel FPGA mapping scheme for multi-output logic units, aiming to improve synthesis performance significantly. By introducing new metrics functions, k-input l-output cut (kl-cut) generation method, and methods to add secondary LUT outputs, the proposed approach enables thorough exploration of the design space. Results show that the proposed dual-output LUT synthesis method achieves 30.2% and 34.7% reduction in LUT usage and depth, respectively, outperforming leading-edge dual-output mapping tools. In addition, the proposed mapping scheme is applied to an emerging field-programmable unit, MCluster, proving compatibility and efficiency on non-LUT logic blocks. For the first time, we perform a system-level design flow to demonstrate the benefit of multi-output LUT at the system level and provide critical insights and design trade-offs.