Design of a High-Precision Relaxation Oscillator with Low Power Dissipation

This design employs a simple comparator-based relaxation oscillation structure, which reduces the overall circuit power consumption. Additionally, it incorporates a negative feedback loop that automatically adjusts the output frequency of the oscillator, thereby mitigating the interference of power supply noise on the output. This results in precise clock cycles and generates an accurate duty cycle through the relaxation oscillation topology. The design utilizes a $0.18 \mu \mathrm{~m} 30 \mathrm{~V}$ BCD process and operates at a supply voltage of 5 V, achieving an oscillator period of 410 ns with a power consumption of $27.8 \mu \mathrm{~A}$. The frequency variation from 3 V to 7 V is measured at only $0.7 \%$. Simulation results indicate that this structure exhibits both low power consumption and minimal power supply sensitivity.