Performance Investigation of a Novel Ferroelectric-Drain Underlap Negative Capacitance Tunnel Field-Effect Transistor

In this paper, a negative capacitance tunneling field-effect transistor with ferroelectric-drain underlap structure (FDU-NC-TFET) is proposed and its performance is simulated by using Sentaurus TCAD. Compared with traditional TFET and NC-TFET devices, FDU-NC-TFET shows a steeper subthreshold characteristic due to its flatter channel energy band distribution. Under the condition of a 0.5 V drain voltage, its subthreshold swing can reach $21.2 \mathrm{mV} / \mathrm{dec}$, which is $37 \mathrm{mV} / \mathrm{dec}$ and $16 \mathrm{mV} / \mathrm{dec}$ lower than that of traditional TFET and NC-TFET, respectively. On the other hand, by introducing the ferroelectric-drain underlap design, the proposed device significantly reduces the gate-drain capacitance, thereby effectively suppressing the negative differential resistance effect in the negative capacitance transistor and further improving the saturation current of the device. Finally, we conducted an analysis of the influence of the ferroelectric-drain underlap parameters, further revealing the unique advantages of the proposed structure in performance optimization.