Greyhound: A Reconfigurable and Extensible RISC-V SoC and eFPGA on IHP SG13G2

Open-source chip design gained increasing attention in recent years. It can play a crucial role in educating the next generation of chip designers by making the designs, EDA tools, and PDKs available to a broad community. In light of this, we present Greyhound, an open-source, reconfigurable, and extensible RISC-V SoC and eFPGA with a focus on educational purposes. Compared to other designs, Greyhound is fully open-source, including the source code, the tools used, and the physical design implementation. With it, students can learn how to program a RISC-V CPU, implement custom instruction extensions and peripherals, or dive into the chip design of Greyhound itself. The SoC achieves a maximum clock frequency of 55 MHz (typ.) and is based on the CV32E40X RISC-V core. It contains 8 KiB of SRAM, a QSPI XIP flash controller, a QSPI PSRAM controller, and UART. The eFPGA is based on the FABulous framework and features 32×I/O, 784×LUT4+FF, 98×MUX, 7×SRAM (4KiB), 7×MAC, and 14×register file. In addition to being used for custom instructions or accelerators, it can be used stand-alone. The final chip is 3.6mm×5mm in size and DRC and LVS clean. Greyhound was taped out in April 2025 through an IHP Open MPW shuttle.