A Low-Jitter Fractional-N Digital PLL Using a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial-Based LMS Calibration

This work presents a 10.0–11.5-GHz fractional- $N$ digital phase-locked loop (DPLL) using the quantization-error-compensating bang–bang phase detector (QEC-BBPD) that can minimize both the static delay ( $T_{\mathrm {S}}$ ) and the dynamic delay ( $T_{\mathrm {D}}$ ) required for removing the delta-sigma modulator’s ( $\Delta \Sigma $ M) quantization-error (Q-error). Since the proposed QEC-BBPD reduces additional thermal noise during the Q-error-compensation process, it allows the DPLL to achieve low in-band phase noise (PN) and low rms jitter. Along with the QEC-BBPD, this work also presents the orthogonal-polynomial-based least-mean-square multivariable calibration (OP-LMS MVC) to accelerate the calibration speed for the removal of the nonlinearities (NLs) of the QEC-BBPD with minimal hardware overhead. The fractional- $N$ DPLL in this work, fabricated in a 40-nm CMOS process, occupied 0.12 mm² of silicon and consumed 14.4mW of power. The rms jitter and worst fractional spur were 64 fs and −62.8 dBc, respectively, at a fractional- $N$ frequency near 10.9 GHz. It achieved the lowest in-band PN and the best normalized jitter-power figure-of-merit for the multiplication factor $N$ (FoM ${}_{\mathrm {jitter,}N}$ ), i.e., −272.2 dB, among the state-of-the-art fractional- $N$ phase-locked loops (PLLs).