A 18.3-ENOB $160.2-\mu \mathrm{W}$ Fully Dynamic Discrete-Time Delta-Sigma ADC Using Floating Inverter Amplifiers

This paper presents a fourth-order discrete-time delta-sigma modulator that employs a two-stage floating inverter amplifier (FIA) in the first integrator. The first integrator utilizes a two-stage FIA with a DC gain of up to 74 dB, while the subsequent three integrators employ simple FIAs with a DC gain of up to 40 dB. The modulator coefficients are meticulously optimized to ensure a lower output swing at each stage, making the design particularly suitable for modulators. The proposed design is fabricated using a 180 nm CMOS process with a supply voltage of 1.8 V. Tested under a sampling frequency of 2 MHz, an OSR of 128, and an input signal amplitude of −5 dBFS, the modulator achieves a power consumption of only $160.2 \mu \mathrm{W}$. Simulation results indicate that the modulator achieves a signal-to-noise-and-distortion ratio (SNDR) of 112.1 dB, a spurious-free dynamic range (SFDR) of 118.19 dB, and a Schreier figure of merit (FOM) based on SNDR of 188.98 dB.