Synthesis of a Self-Timed Pipeline by Converting the Description of a Synchronous Analog

Automatic synthesis of digital circuits is a necessary tool that ensures an acceptable level of production cost and widespread application. Currently, the focus of digital circuit design is increasingly shifting from synchronous design towards asynchronous techniques and its subclass — self-timed (or delay-insensitive) design. Asynchronous design theoretically enables higher energy efficiency and reduces the complexity of constructing a clock tree in a digital circuit. Self-timed design, in turn, further improves energy efficiency, eliminates the need for a clock tree, and provides inherent testability, thereby increasing the reliability of the digital circuit. Over the past two decades, several methods and software tools have already been proposed to automate the synthesis of asynchronous circuits. This paper presents a method for automating the synthesis of a circuit in the form of a self-timed pipeline by converting an initial synchronous description. The method allows partitioning the original circuit into synchronous and self-timed subcircuits and includes the synthesis of an interface for their interaction. Key stages of the method include determining the boundaries of the synchronous pipeline and forming a request-acknowledge control mechanism for its operation.