Integer Division Algorithm for the Gaussian Filtering Module of FPGA Based Edge Detection

In the speed domain, integer division is a critical problem to FPGA based edge detection which uses Gaussian filtering. Solving this problem requires the design of an FPGA focused integer division algorithm that satisfies two major goals in terms of speed: 1) work at a frequency that vastly exceeds the upper limit of execution speed in FPGA based edge detection – the highest clock frequency of embedded memory; 2) guarantee mathematically accurate result within a single clock cycle. This is what the presented paper focuses on to investigate by involving ten Intel (Altera) FPGA families.