Patterns that Break Memory: SEU Characterization of COTS LPDDR2 and LPDDR4 SDRAM via Stress Testing Under 60 MeV Proton Beam

As DRAM scales to smaller nodes, commercial off-the-shelf (COTS) memory achieves higher density and lower cost but faces increased inherent single-event upset (SEU) susceptibility, complicating the adoption of energyefficient Low-Power Double Data Rate (LPDDR) SDRAM, ideal for power-constrained satellites like CubeSats. Radiationhardened memory, while more SEU-resistant, is increasingly becoming impractical for modern space systems due to lower bit density, higher cost, and infeasibility with computeintensive tasks like AI/ML applications. Additionally, limited public SEU radiation test data on LPDDR devices, particularly for emerging failure modes, constrains reliability assessment of COTS ECC adequacy in masking radiation-induced memory faults. This also hinders the development of fault-tolerance measures that could enable wider LPDDR adoption in space systems through improved reliability. In this paper, we evaluate the SEU susceptibility of COTS LPDDR memory through proton irradiation tests using 20-58 MeV proton beams on two architecturally distinct SoC platforms: the Raspberry Pi Zero 2 W (512 MB LPDDR2 SDRAM) and the NXP i.MX 8M Plus (4096 MB LPDDR4 SDRAM). Constant memory stress testing through Linux during irradiation exposed several previously unreported failure modes, including SBUs, MBUs, row-hammer faults, and stress-ng-detected modulo-x, gray code, rand-set, and modulo X faults. The resulting dataset provides key insights for COTS ECC optimization and informs the suitability of LPDDR for modern space systems.