Towards a validated core memory model through (MP)SoC events

The certification of safety-critical systems requires amongst other things understanding the underlying hardware platform, and its use in the context of the system. At the processor level, it means that the designer must understand in detail the behaviour of a core executing a program. Many approaches rely on capturing such knowledge in an abstract model of the core. A crucial question is then does the model correctly represent the processor? and how can the designer prove such correctness? In this paper, we propose a methodology to build a core model, taking solely into account the memory accesses, and to validate the resulting model with associated stressing benchmarks.