Modeling and Analysis of Speed Control Loop for Low Carrier Ratio PWM CSI-fed Motor Drives Based on Discrete-Time State Space Equation

The traditional engineering speed loop modeling and analysis simplifies the control loop by considering the inner current control loop as first-order lag without considering the dq-axis cross coupling issue of inner control loops, which is not suitable for low carrier ratio applications with distinct delay effect and cross-coupling issues. Aiming at this problem, this paper establishes the inner control loop based on discrete-time state space equation, which fully reflects the impact of the dq-axis cross coupling issue caused by synchronous rotating coordinate transformation as well as the huge digital delay caused by low carrier ratio for PWM current source inverter (CSI)-fed motor drives. Then, an accurate outer speed control loop is established by cascading the inner control loop with the speed controller. The proposed speed control loop model can provide a theoretical basis for analyzing system stability and dynamic performance of PWM CSI-fed drive system with low carrier ratio. The correctness of the modeling methodology is theoretically supported by analysis of root locus diagram and experimentally verified on a laboratory prototype.