BDD Meets SAT: Binary Hybrid Diagrams for Efficient Generation of Multiple Solutions

The hardware complexity in electronic devices has increased significantly in recent decades due to technological advancements. To ensure correct behavior of such devices and meet time-to-market constraints, modern circuit verification and testing tools rely on formal proof techniques. The two most popular methods in this context are Binary Decision Diagrams (BDDs) and Boolean Satisfiability (SAT) solvers. Even though these methods share some similarities, they are fundamentally different. Whereas BDDs usually require a large amount of memory to represent all solutions, SAT solvers are memory-efficient but they typically compute only a single solution. To tackle these issues, a hybrid approach called Binary Hybrid Diagram (BHD) is proposed for efficient generation of multiple solutions. BHDs combine the major advantages of BDDs and SAT solvers, and generate distinct solutions heuristically via algorithms. Experiments demonstrate that feasible solutions are generated rapidly by using BHDs while the memory requirement remains small compared to state-of-the-art methods.