A 22.4-to-35-GHz Two-Stage Low-Noise Amplifier With Triple-Coupled Transformer-Based Input Matching Technique in 65-nm CMOS

This article presents the analysis and design of a two-stage low-noise amplifier (LNA) with enhanced wideband input matching bandwidth and a low flat noise figure (NF) across the entire operating range. A compact triple-coupled transformer-based input power matching network is proposed to facilitate broadband input and noise matching simultaneously. In addition, by accounting for the loading effect of the interstage magnetically coupled resonator (MCR), a third peak of input impedance is achieved for further bandwidth extension. Designed and fabricated in a 65-nm CMOS process, the proposed LNA achieves a 3-dB bandwidth from 22.4 to 35 GHz with a gain of 12.0 dB. The 10-dB input return loss bandwidth is 33.7 GHz, spanning from 14.9 to 48.6 GHz. The measured NF is between 2.7 and 3.2 dB, and the input 1-dB gain compression point (IP_1dB) ranges from −12.5 to −10.6 dBm. The measured third-order input intercept point (IIP₃) is −0.7 dBm at 28 GHz. The LNA consumes 11.3 mW and occupies a core area of 0.15 mm².