An Embedded RISC-V Vector Processor for Energy-Efficient GNSS Signal Processing and Navigation Computation

The on-chip processor of modern high-precision Global Navigation Satellite System (GNSS) receiver chips is required to perform signal processing and navigation computations for multiple signal channels within a tight time window, which imposes high demands on computational power. Existing GNSS receiver chips typically address these challenges by stacking multiple processor cores or designing custom hardware; however, such solutions have limitations in area, power, and generality. This work proposes a vector processor architecture based on the RISC-V Vector Extension (RVV) and evaluates vectorization optimizations for several key GNSS algorithms. Compared to the baseline, this work achieves a 6.13× speedup and a 3.02× improvement in energy efficiency (EE) for the tracking loop processing (TLP) algorithm, and a 5.83× speedup for the Newton-Raphson (NR) method used in navigation computation. Given the general-purpose advantages of the RVV architecture, the proposed vector processor also holds potential for optimizing other algorithms involved in GNSS receiver systems.