Process-Induced Warpage Behavior in Backside Power Delivery Network Fabrication

As semiconductor devices continue to scale, backside power delivery networks (BSPDNs) have emerged as a promising alternative to conventional front-side power delivery networks (FSPDNs), offering improved routing flexibility and power integrity. However, BSPDN integration introduces significant thermo-mechanical challenges, particularly wafer warpage induced by material and structural asymmetry. In this study, wafer warpage evolution during key BSPDN fabrication steps is investigated using calibrated three-dimensional finite element method (FEM) simulations. Warpage increases progressively throughout processing, reaching a convex value of +448.55 lm after high-pressure annealing (HPA), identified as the most critical stage driving final deformation. Analysis of Cu crystal orientations (100, 110, 111) shows only minor variations in warpage, whereas BSPDN Cu interconnection density has a more pronounced influence. Increasing Cu density amplifies thermal expansion mismatch in the backside stack, leading to greater stress accumulation during heating; during HPA, the warpage changes by about 7.41% as Cu interconnection density increases from 40% to 90%. Comparison between FEM results and analytical predictions from Suhirs model shows close agreement, validating the mechanical interpretation. These findings provide a predictive framework for understanding BSPDN-related warpage and offer guidance for layout and process optimization in advanced packaging.