Signal Integrity Analysis of Interconnect Structures in 2.1D Thin Film Packaging for Chiplet Integration

As semiconductor process nodes approach physical limitations, advanced packaging technologies— especially chiplet-based integration—are emerging as a promising solution to improve computational performance while reducing cost and maintaining yield. The Universal Chiplet Interconnect Express (UCIe) standard offers a reference framework for chiplet interconnection, supporting both 2D and 2.5D integration. However, the high cost and limited supply chain of silicon interposers in 2.5D packaging prompt exploration of alternatives such as 2.1D System-In-Package (SiP) structures, which leverage thin film layers on traditional substrates. This study investigates signal integrity within 2.1D packaging, focusing on micro-bumps, vias, and inter-layer traces in thin film interconnect channels. Using full-wave simulations with HFSS, the effects of bump pitch, via height, pad size, and trace structutre on transmission characteristics and crosstalk were analyzed. Simulation results show that shrinking bump pitch from 55 µm to 35 µm can improve insertion loss and reduce near-end crosstalk due to enhanced coupling with ground bumps and reduced bump height. Via simulations indicate negligible resonance below 30 GHz and increased crosstalk with taller dielectric layers. Furthermore, thin film traces in a 2-layer stripline configuration demonstrated lower crosstalk compared to silicon interposer routing, attributed to the lower dielectric constant of the polymer materials used.This work provides a comprehensive parametric analysis of key interconnect structures in 2.1D thin film packaging and offers practical insights for improving signal integrity in chiplet-based microsystem designs.