Thermal Reliability Analysis and Optimization of Millimeter-Wave Multi-Chip RF Front-End Modules based on Heterogeneous HDI substrate

To address reliability challenges from high integration of 5G/6G RF front-end microsystems, this study optimizes electrothermal performance and predicts solder joint fatigue life in 3D stacked heterogeneous packages. A 3D model incorporating ABF/LCP/PP dielectric layers was established, revealing a CMOS chip temperature of 47.02 °C . Through spatial layout optimization, the maximum temperature was reduced to 36.8 °C , marking a 37.8% decrease. Utilizing the Darveaux model, the fatigue life of SAC305 solder joints was quantified, with corner ball grid array joints, which are susceptible to multi-directional thermal stress, exhibiting a minimum failure cycle of 13,840. Submodel analysis unveiled uneven weld stress, with a maximum value of 15.5 MPa. The interface thin-layer failure cycles (1955.2) were significantly lower than those of the ball body (15484). Submodel validation confirmed high consistency (error <5%) with the full model in terms of temperature, energy dissipation, and strain, thereby ensuring the reliability of the predictions.