Design and Verification of Fan-Out on Substrate Package Interconnects Based on UCIe

This paper presents the design, fabrication, and validation of UCIe-compliant interconnect structures using a Fan-Out on Substrate (FOoS) packaging platform, combining wafer-level fan-out (WLFO) redistribution layer (RDL) interconnects and flip-chip ball grid array (FCBGA) substrates. WLFO RDLs are optimized for UCIe-A short-reach communication, achieving high signal integrity through microstrip and staggered microstrip structures with an edge bandwidth density of up to 5.27 Tbps/mm. FCBGA interconnects are designed for UCIe-S long-reach transmission, reaching 3.58 Tbps/mm, with controlled-impedance stripline routing. Full-wave electromagnetic simulations and experimental validations, including S-parameter measurements, VTF analysis, and eye diagram testing, confirm compliance with UCIe’s stringent 32 Gbps requirements. The proposed interconnect schemes offer a high-bandwidth, scalable solution for chiplet-based heterogeneous integration, supporting the development of next-generation high-performance computing and advanced packaging technologies.