Ultra-Low Latency Generalized Architecture for Complex Nth Root and Nth Power Computation

This paper proposes a novel computing architecture for high-precision, low-latency, low-power, and cost-effective computation of complex number Nth roots and Nth powers. By integrating the high-precision properties of the coordinate rotation digital computer (CORDIC) algorithm with the low-latency benefits of piecewise linear (PWL) approximation, the architecture leverages the binary logarithm-antilogarithm relationship to compute roots and powers of arbitrary complex numbers. Specifically, The Nth roots and Nth powers of the modulus of the input complex number are computed using normalization preprocessing and PWL, and the conversion between the plane coordinate and polar coordinate forms of the complex number is achieved using the CORDIC algorithm. The design is implemented in Verilog HDL and synthesized using 40nm CMOS technology at a frequency of 1GHz. The synthesis results show that the area consumption for the complex Nth root computation is $24193.92\mu $ m², with a power consumption of 2.1352mW. The area consumption for the complex Nth power computation is $20836.83\mu $ m², with a power consumption of 1.8658mW. Compared to the latest complex Nth root design, the proposed architecture reduces the area by 11.67% and power consumption by 9.33%. The average accuracy exhibits only a slight reduction compared to the state-of-the-art design while remaining at the same order of magnitude. Furthermore, the computation delay for the Nth root architecture is only 58.46% of the delay of the latest complex Nth root design, while the delay for the Nth power architecture is 94.87% of the delay of the existing real-valued Nth power design.