Fully Integrated Two-phase Dual Rails Charge Pump Design in Gate-all-around (GAA) Ribbon FET process technology

This paper presents fully integrated two-phase dual rails charge pump designs generating Vin_cp and Vss_cp, which are ~100 mV-150 mV above and below supply rail Vin and ground rail Vss, respectively. Designed for MOSFET channel leakage reduction in a voltage converter system, these charge pumps are fabricated in Intel’s latest 18A Gate-all-around (GAA) process technology where the channel leakage of MOSFETs is significant. With Vin set at 1.25 V, which is a SoC fixed input supply and a fixed input clock of 100 MHz from SoC, the designs have a nominal voltage ripple of around 25 mVpp. The design proposes a voltage feedback control with state-space averaging based stability analysis. As the electrical-overstress (EOS) limit for Ribbon FET, the type of MOSFET used in intel 18A, is smaller than 1.25 V, intermediate voltages are generated to tolerate Ribbon FETs’ EOS rules, and proper level shifters are applied to the switches and clock propagation circuits. The final design has a measured maximum current load of ~300 μA and a voltage droop or voltage overshoot from no load to the maximum load of within 40 mV. It also achieves the highest output current density among previous works.