TOPS: Topology-Based Partial Scan for Stuck-At and Delay Testing

Partial scan design reduces the shortcomings of full-scan design while retaining its advantages by selectively converting flip-flops in a circuit. In many cases, specific flip-flops cannot be converted to scan cells due to design constraints. In this paper, a topology-based partial scan method is proposed to consider both stuck-at and delay testing. The need for delay testing is growing, yet conventional partial scan methods are ineffective for delay fault models. The proposed method should consider not only stuck-at fault models but also delay fault models. The proposed method introduces three processes. First, controllable flip-flops are selected for the shift operation without reducing circuit controllability. Second, observable flip-flops are selected for the capture operation without reducing circuit observability. Third, a logic topology-based algorithm is applied to ensure that both stuck-at and delay testing are considered in the selection process. As a result, the chosen flip-flops preserve controllability and observability close to that of a full-scan design, allowing the partial scan to remain effective for delay testing. Experimental results show that the proposed method achieves higher test coverage than the previous methods and enables efficient scan-based testing for both stuck-at and transition-delay fault models.