A −53.7-dB PSRR, Fast-Transient Output-Capacitor-Less Digital-Assisted Analog LDO Using Seamless Digital-to-Analog Transfer Technique

This work presents an output-capacitor-less digital-assisted analog low-dropout regulator digital-assisted analog LDO (DA-ALDO) that employs a seamless digital-to-analog transfer (D2A-TF) technique enabled by a local ground generator (LGG). The proposed architecture extracts only the strengths of digital LDOs (DLDOs)—fast transient response and low voltage droop—and analog LDOs (ALDOs)—high power supply rejection ratio (PSRR)—to achieve an optimized performance without inheriting their drawbacks. The proposed DA-ALDO is fabricated in a 28-nm CMOS process and achieves a PSRR of −57.6 and −53.7 dB at 10 kHz under load currents of 1 and 100 mA, respectively. It exhibits a voltage droop of only 54mV and a fast settling time of 667 ns in response to a 99-mA load step while consuming a quiescent current of $338.5~{\mu }$ A. The regulator occupies a compact active area of 0.032 mm² and achieves a figure of merit (FoM) of 0.029 ps.