Implementation of LowCost Time-to-Digital Converter in the off-theshelf Radiation-Tolerant Space-Grade FPGA

In this article, we present an approach to implementing a high-resolution Time-to-Digital Converter (TDC) in a radiation-tolerant FPGA. The system is specifically designed for space environments such as readout electronics for telecom single photon receivers and satellite Quantum Key Distribution (QDK) systems, enabling stable optical communication over long distances, reception of the quantum key or periodic recalibration of quantum key sources in orbit. The paper comprehensively overviews the challenges and methods related to implementing Tapped Delay Line (TDL) TDCs on FPGAs and describes a system design using this approach on the RTG4 FPGA. To compute the characteristic, a statistical delay calibration method was used and utilized during post-processing of the data. The system has been implemented using a commercial design kit and a custom-built expansion board and achieves 5 ps mean resolution with 100 MHz sampling clock. High temporal resolution not only enhances the accuracy of quantum photon pair detection but also significantly contributes to the robustness and longevity of outer space single photon communication systems. The choice of RTG4 FPGAs, which are widely used in space, enables easy deployment of the proposed solution in a variety of space communications applications.