SiGe Channel Trench-Free Complementary FET With Direct Backside Contact for Suppressed Process Variation and High-Speed Applications

In this article, a novel SiGe channel trench-free complementary field-effect transistor (TF-CFET) with direct backside contact (DBC) is proposed for the first time. Compared to conventional complementary FET (CFET) with trench height ( ${H}_{\text {Tr}}\text {)}$ of 30 nm, TF-CFET demonstrates 21.0% reduction in ${C}_{\text {GG}}$ with the same dc performance. This can be attributed to the removal of the trench under the SiGe channels of bottom pMOS, which significantly reduces the area of ${C}_{\text {GS}}$ . Moreover, due to the absence of etching stop layer during the source/drain (S/D) recess, the over-etching thickness ( ${T}_{\text {SD}}\text {)}$ has significant impact on dc and ac performance of traditional CFET. However, TF-CFET demonstrates perfect immunity to ${T}_{\text {SD}}$ variations. Additionally, the inverter, ring oscillator (RO), and static random access memory (SRAM) are investigated to further evaluate the ac performance of TF-CFET. The results show that, compared to the CFET with ${H}_{\text {Tr}}$ of 30 nm at ${V}_{\text {DD}} =0.7$ V, TF-CFET achieves 5.0% (7.1%) reduction in inverter rise (fall) time, 14.7% improvement in RO frequency, and 8.6% (11.1%) decrease in SRAM read (write) delay. Therefore, TF-CFET not only demonstrates enhanced capability in suppressing process variations but also is suitable for high-speed applications.