Digital Pulse-Width Modulation Circuit Design Using Large Language Models

The escalating complexity of modern digital systems has imposed significant challenges on Integrated Circuits (ICs) design, necessitating tools that can simplify the IC design flow. The advent of Large Language Models (LLMs) has been seen as a promising development, with the potential to automate the generation of Hardware Description Language (HDL) code, thereby streamlining digital IC design. However, the practical application of LLMs in this area faces substantial hurdles. Notably, current LLMs often generate HDL code with small but critical syntax errors and struggle to convey the high-level semantics of circuit designs accurately. These issues significantly undermine the utility of LLMs for IC design, leading to misinterpretations and inefficiencies. In response to these challenges, this paper presents targeted strategies to harness the capabilities of LLMs for digital ASIC design. A three-phase digital Pulse-Width Modulation (PWM) circuit was designed and implemented using the proposed strategies as part of the Efabless AI-Generated Open-Source Chip Design Challenge. The design passed Design Rule Check (DRC) and was fabricated successfully. The HDL codes for the design were 100% generated by LLM prompts. Evaluation of the three-phase digital PWM shows a 120° phase differences and full range of programmable duty cycle (0% - 100%).