An on-chip all-digital low-mismatch CMOS process monitoring sensor circuit for accurate process sensing in 28-nm FD-SOI technology

As semiconductor manufacturing processes continue to scale down, variability-induced process shifts have become a significant challenge, impacting both yield and performance of a chip. Die-Die and within-die process variations can occur during the manufacturing cycle of a silicon wafer leading to mismatches in electrical parameters of circuits thereby impacting the performance and power of a chip. To mitigate the impacts of these variations, larger guard bands during circuit design are taken leading to performance and area loss. To improve yield and reduce design margins, information regarding the process centering of a silicon die therefore becomes crucial. This paper proposes an on-chip all-digital low mismatch sensor circuit to monitor ON-current variations of nMOS and pMOS independently. The dependency of ON-current on threshold voltage makes this circuit useful for sensing process variations. The proposed architecture enables high sensing accuracy and area efficiency by using an inverter-based topology. For a 60 stage sample size for nMOS and 84 stage for pMOS, the sensor area is 0.00096 mm² with worst-case standby power consumption of 600 μW at 0.8 V operation. The solution therefore enables low-cost implementation for applications such as post-silicon tuning using adaptive voltage scaling, adaptive body-bias and to validate model accuracy through model vs silicon mismatch. Detailed simulation and silicon results in 28-nm Fully Depleted Silicon on Insulator (FD-SOI) show the validity of the proposed circuit.