Performance Enhancement of Schottky Barrier MOSFET by Laser-Induced Low Temperature Dopant Segregation for Monolithic-3D Integration

Monolithic 3-Dimensional (M3D) integration has emerged as a promising approach to extend Moorefs Law. However, overcoming the thermal limitations associated with fabricating top-tier devices remains a significant challenge. In this study, laser-induced silicide dopant segregation (LSDS) source/drain (S/D) technology is explored to optimize the performance of low thermal budget (Low-TB,≤500∘C for 2 hours) Schottky Barrier MOSFET fabricated as top-tier devices for M3D integration. A nanosecond-pulsed green laser is employed to induce dopant segregation in Schottky S/D regions, resulting in a sharpened interface with a high Schottky barrier and elevated impurity concentration. This process enables the fabrication of high-performance CMOS devices, achieving ION> 100 μA/μm at LG = 500 nm with limited variation. Experimental results show that the S/D series resistance is reduced by 28.7% and 11.9% for N and P MOSFETs at 1.0 J/cm2 compared to the conventional rapid thermal annealing (RTA) process. Furthermore, inverters, ring oscillators, and logic gates are successfully demonstrated, showing the multi-functionality of this approach and its potential as an alternative fabrication scheme for M3D circuit applications.