Design and Implementation of Approximate Multiplier Using Approximate 4-2 Compressors and Approximate Half Adders

In real-time Advanced computing applications such as image processing, neural networks and digital signal processing (DSP), Approximate multipliers are designed to provide acceptable results while conserving power, hardware resources and improving speed with bounded inaccuracies. In this paper we design an Approximate Multiplier using Approximate compressor and Approximate Half Adders to gain less power consumption for approximate computing. The experimental results indicate $89.47 \%$ decrease in area, $86.82 \%$ decrease in power and $48.057 \%$ decrease in the area delay for proposed $8 \times 8$ multiplier compared to exact multiplier. The accuracy percentage for the proposed multiplier is $77.5 \%$. The proposed design is coded in Verilog HDL and simulated using Xilinx VIVADO tool.