Coordinating Binary Trait: Accurate and Lightweight Runtime On-Chip Power Meter Design

As heterogeneous platforms scale, power management issues grow increasingly critical. On-chip power awareness is fundamental to effective power management on such platforms. However, the integration of diverse components leads to higher power consumption and more complex power patterns, complicating the perception of power distribution. To address this challenge, this article presents COordinating BInary Trait (COBIT), which focuses on the design and optimization of on-chip power meters (OPMs) for heterogeneous design, enabling power management in large-scale systems. COBIT extracts essential bitwise wires as features, learns a boosting model based on binary trees, and implements the OPM for runtime power prediction. Additionally, multiobjective optimization algorithms are employed in the design space exploration of the power meter to ensure an accurate and low-overhead integration. Experimental results demonstrate the capabilities of COBIT on heterogeneous hardware. Using only 0.028% bitwise power proxies of all RTL wires in the NVIDIA deep learning accelerator (NVDLA) and 0.036% in the Berkeley out-of-order machine (BOOM) processor core, the per-cycle models achieve a mean absolute percentage error (MAPE) of 1.69% and 2.49%, respectively. Regarding the success rate of predictions on power peaks in NVDLA, COBIT achieves a maximum performance improvement of 12.93% and an average improvement of 8.11% over existing methods. Moreover, the gate-area/power overhead of our OPM on BOOM and NVDLA is 1.25%/0.217% and 0.49%/0.097%, respectively, while performing per-cycle power prediction in just three cycles. Unlike previous approaches, which struggle with balancing accuracy and efficiency, COBIT effectively addresses both challenges, delivering unprecedented benefits for large-scale systems.