Inductorless 5.405 GHz Fractional-N PLL for RF Synthesis with 5.6 mW Power Consumption

For energy-efficient RF synthesis in IoT and mobile applications, this work introduces an enhanced Fractional-N Phase-Locked Loop (PLL) architecture. The design achieves a power consumption of less than 5.6 mW while delivering superior performance in terms of phase noise and loop bandwidth. To mitigate $\Delta \Sigma$ quantization noise, a novel adaptive digital noise filter is implemented, replacing the conventional synchronous delay line. A multi-loop PLL structure is incorporated to improve frequency accuracy and minimize jitter. Furthermore, a high-resolution digital phase detector (DPD) is utilized to reduce phase variation. Implemented in a 180 nm CMOS process, the PLL exhibits an in-band phase noise of less than $-105 \text{dBc} / \text{Hz}$, an integrated jitter of approximately $1 \text{ps}_{\text{rms}}$, and a loop bandwidth exceeding 15 MHz. These results demonstrate the proposed PLL's suitability for high-precision, low-power wireless communication systems.