CFcoQUIC: CPU/FPGA Co-design Accelerated QUIC for Low-Power IoT Communication

In IoT environments, devices are often constrained by low power consumption and limited resources, making efficient connection establishment with minimal overhead crucial for real-time communication between edge devices and cloud servers. The QUIC protocol shows significant potential, but the encryption and decryption overhead is considerable. Reducing this overhead and improving connection establishment efficiency are critical to enhancing QUIC performance, especially for IoT edge devices that need to handle high-concurrency communication while maintaining low power consumption. This paper proposes CFcoQUIC, a CPU/FPGA co-design architecture that accelerates the handshake process and reduces the initial connection latency by parallelizing multiple encryption/decryption flows in high-concurrency environments. Experimental results demonstrate that the time for RSA encryption and decryption on FPGA is at least 19.1 times faster than on CPU, and the time for AES encryption and decryption is at least 5 times faster on FPGA. These results highlight the effectiveness of the proposed architecture in reducing QUIC handshake overhead in IoT environments with low-power edge devices.