MergFS: Efficient Bridging of a 32-bit High-Speed Intra-Core Bus to a 64-bit Low-Speed AHB-Lite Bus

In the architecture of system-on-chip (SoC) design, the bus plays a critical role by facilitating inter-module connections and managing data transmission. Although the commercial bus solutions represented by the Cortex-M System Design Kit (CMSDK) are widely adopted in the industry, they exhibit lower communication efficiency in certain specialized requirements. This research focuses on optimizing the transition from a 32-bit high-speed intra-core bus to a 64-bit low-speed AHB-Lite bus. A new solution (MergFS) for this conversion process is proposed and implemented, which supports request merging and dynamic frequency switching. Experimental results show that, compared to the solution using CMSDK, MergFS reduces clock cycles by approximately 50% to 75% when processing multiple transactions. Additionally, synthesis results under the three different technologies show MergFS introduces ~4.5% area and ~6.02% power overhead on average.