TransRoute: A Novel Hierarchical Transistor-Level Routing Framework Beyond Standard-Cell Methodology

In advanced technology nodes, benefits from scaling have become limited in terms of power, performance, and area (PPA), necessitating improvements through design-technology cooptimization (DTCO). While the standard-cell methodology is widely used in modern VLSI design, it inherently constrains the potential of DTCO due to its abstraction at the logic level, limiting optimization at the physical level. To bridge this gap, transistor-level design methodology is desired to break the abstraction of standard cells. Existing research has explored large-scale transistor placement, but a gap remains in developing a routing framework that efficiently addresses transistor-level routing challenges. This paper proposes a pioneering transistorlevel routing framework for large-scale transistor placements, along with an efficient CP-SAT (Constraint ProgrammingSATisfiability) formulation for routing in lower layers. Experimental results demonstrate that the proposed routing framework enables transistor-level designs to achieve significantly reduced total wirelength and high utilization rates for designs with hundreds to thousands of transistors, outperforming traditional standard-cell-based approaches in advanced technology nodes.