Antenna Design & Simulation with shorting pin for AIS Application

This paper represents the design and simulation of antenna with shorting pin for AIS Application. The antenna is designed with a vertically stacked patch array. Both designs utilize FR4 substrates of dimensions 46 x 17 cm. The stacked antenna design incorporates a 1.5 cm air gap between the layers, with the parasitic patch and substrate shorted to the driven patch via a shorting pin for enhanced coupling and performance. The stacked antenna demonstrates an S11 of -20.3 dB, gain of 2.15 dB and a bandwidth of 12.5 MHz at operating frequency of 161MHz frequency which is used for AIS Application. As compared to other antennas operating at 161 MHz and used for AIS Applications, proposed stacked structure gives enhancement in gain. The results confirm that the stacked design achieves better performance while maintaining compactness, making it a viable candidate for applications like Automatic Identification Systems (AIS).