A 0.3 V Ultra-Low Power Hysteresis Comparator With SRAM-Based Output Stage and Its Application in Asynchronous Sigma-Delta Modulators

This work presents a novel hysteresis comparator for ultra-low voltage asynchronous sigma-delta modulators, featuring a regenerative bulk-based SRAM output stage that enables rail-to-rail operation and significantly improves speed through positive feedback. Nominal simulations on TSMC 180 nm technology show a delay of 35.91 $\mu $ s, power dissipation of 7.27nW, and a hysteresis threshold of 4.24mV. The comparator demonstrates strong robustness under PVT and mismatch variations, with limited degradation in speed and hysteresis control. Analytical models for the hysteresis behavior and the comparator’s delay, based on small-signal approximation, have been developed and validated through simulations, showing close agreement. Compared to state-of-the-art design, the proposed solution achieves up to $2\times $ faster delay, lower power, and more stable hysteresis across operating conditions. Monte Carlo analysis further confirms its resilience to mismatch, with minimal variations regarding the hysteresis threshold. Performance improvements of the proposed comparator have been also tested in a real-case application scenario, integrating it in an asynchronous sigma-delta modulator from the literature. The results of the post-layout simulations show an improvement in the bandwidth and in the effective number of bits, with a consequent improvement in the value of the figure of merit, which goes from 0.76 pJ/step for the referenced literature solution to 0.31 pJ/step for the proposed solution. These results confirm the proposed comparator as a competitive topology for low-power, low-voltage analog systems, especially in biomedical and IoT applications.